We present a systematic approach to decompose and incrementally build the proof of correctness of pipelined microprocessors. The central idea is to construct the abstraction function by using completion functions, one per unfinished instruction, each of which specifies the effect (on the observables) of completing the instruction. In addition to avoiding the term size and case explosion problem that limits the pure flushing approach, our method helps localize errors, and also handles stages with interactive loops. The technique is illustrated on pipelined and superscalar pipelined implementations of a subset of the DLX architecture. It has also been applied to a processor with out-of-order execution
We present a collection of ideas that allows the pipeline verification method pioneered by Burch an...
This paper demonstrates the modeling and deductive verification of out-of-order microprocessors of v...
Presented here is a formal specification and verification of a property of a quadruplicately redunda...
technical reportWe present a systematic approach to decompose and incrementally build the proof of c...
In microprocessors, achieving an efficient utilization of the execution units is a key factor in imp...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2]...
The following topics are covered in viewgraph form: (1) generic interpreters; (2) Viper microprocess...
A number of methodologies for verifying systems and computer based tools that assist users in verify...
AbstractWe present a method for pipeline verification using SMT solvers. It is based on a non-determ...
Over the past four decades microprocessors have come to be a vital and inseparable part of the moder...
The Completion Functions Approach was proposed in [HSG98] as a systematic way to decompose the proof...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2...
The paper presents a sequence of three projects on design and formal verification of pipelined and s...
Microprocessor pipelining is a well-established technique that improves performance and reduces powe...
AbstractWe apply algebraic tools for modelling microprocessors to the specification, implementation,...
We present a collection of ideas that allows the pipeline verification method pioneered by Burch an...
This paper demonstrates the modeling and deductive verification of out-of-order microprocessors of v...
Presented here is a formal specification and verification of a property of a quadruplicately redunda...
technical reportWe present a systematic approach to decompose and incrementally build the proof of c...
In microprocessors, achieving an efficient utilization of the execution units is a key factor in imp...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2]...
The following topics are covered in viewgraph form: (1) generic interpreters; (2) Viper microprocess...
A number of methodologies for verifying systems and computer based tools that assist users in verify...
AbstractWe present a method for pipeline verification using SMT solvers. It is based on a non-determ...
Over the past four decades microprocessors have come to be a vital and inseparable part of the moder...
The Completion Functions Approach was proposed in [HSG98] as a systematic way to decompose the proof...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2...
The paper presents a sequence of three projects on design and formal verification of pipelined and s...
Microprocessor pipelining is a well-established technique that improves performance and reduces powe...
AbstractWe apply algebraic tools for modelling microprocessors to the specification, implementation,...
We present a collection of ideas that allows the pipeline verification method pioneered by Burch an...
This paper demonstrates the modeling and deductive verification of out-of-order microprocessors of v...
Presented here is a formal specification and verification of a property of a quadruplicately redunda...