Add to ORKGThe following topics are covered in viewgraph form: (1) generic interpreters; (2) Viper microprocessors; (3) microprocessor verification; (4) determining correctness; (5) hierarchical decomposition; (6) interpreter theory; (7) AVM-1; (8) phase-level specification; and future work
A viewgraph presentation of an automatic code scheme for source verification issues is shown. The to...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2]...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
The Royal Signals and Radar Establishment (RSRE) and members of the Hardware Verification Group at C...
Formal specification combined with mechanical verification is a promising approach for achieving the...
The main goal of the project was two-fold: First, to investigate the feasibility of formally specify...
In microprocessors, achieving an efficient utilization of the execution units is a key factor in imp...
This presentation describes a project, formal verification of the microcode in the AAMP5 microproces...
We describe the formal verification of a hardware subsystem consisting of a memory management unit a...
Over the past four decades microprocessors have come to be a vital and inseparable part of the moder...
The work done at ORA for NASA-LRC in the design and formal verification of a hardware implementation...
By abstracting the details of the data representations and operations in a microprocessor, term-leve...
Abstract—This paper describes the motivation for hy-brid term- and word- level verification models. ...
The formal specification and partial verification of the VIPER microprocessor is reviewed. The VIPER...
We present a systematic approach to decompose and incrementally build the proof of correctness of pi...
A viewgraph presentation of an automatic code scheme for source verification issues is shown. The to...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2]...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
The Royal Signals and Radar Establishment (RSRE) and members of the Hardware Verification Group at C...
Formal specification combined with mechanical verification is a promising approach for achieving the...
The main goal of the project was two-fold: First, to investigate the feasibility of formally specify...
In microprocessors, achieving an efficient utilization of the execution units is a key factor in imp...
This presentation describes a project, formal verification of the microcode in the AAMP5 microproces...
We describe the formal verification of a hardware subsystem consisting of a memory management unit a...
Over the past four decades microprocessors have come to be a vital and inseparable part of the moder...
The work done at ORA for NASA-LRC in the design and formal verification of a hardware implementation...
By abstracting the details of the data representations and operations in a microprocessor, term-leve...
Abstract—This paper describes the motivation for hy-brid term- and word- level verification models. ...
The formal specification and partial verification of the VIPER microprocessor is reviewed. The VIPER...
We present a systematic approach to decompose and incrementally build the proof of correctness of pi...
A viewgraph presentation of an automatic code scheme for source verification issues is shown. The to...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2]...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...