AbstractWe present a method for pipeline verification using SMT solvers. It is based on a non-deterministic “mother pipeline” machine (MOP) that abstracts the instruction set architecture (ISA). The MOP vs. ISA correctness theorem splits naturally into a large number of simple subgoals. This theorem reduces proving the correctness of a given pipelined implementation of the ISA to verifying that each of its transitions can be modeled as a sequence of MOP state transitions
The transition from single-core to multi-core processors has made multi-threaded software an importa...
Our reliance on the correct functioning of embedded systems is growing rapidly. Such systems are use...
The design of concurrent algorithms tends to be a long and difficult process. Increasing the number ...
AbstractWe present a method for pipeline verification using SMT solvers. It is based on a non-determ...
Microprocessor pipelining is a well-established technique that improves performance and reduces powe...
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5970511&tag=1Microarchitectural refinements are...
AbstractWe apply algebraic tools for modelling microprocessors to the specification, implementation,...
technical reportWe present a systematic approach to decompose and incrementally build the proof of c...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2]...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2...
In microprocessors, achieving an efficient utilization of the execution units is a key factor in imp...
Subject of this thesis is the formal verification of pipelined microprocessors. This includes proces...
We present a systematic approach to decompose and incrementally build the proof of correctness of pi...
technical reportWe offer a solution to the problem of verifying formal memory models of processors b...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
The transition from single-core to multi-core processors has made multi-threaded software an importa...
Our reliance on the correct functioning of embedded systems is growing rapidly. Such systems are use...
The design of concurrent algorithms tends to be a long and difficult process. Increasing the number ...
AbstractWe present a method for pipeline verification using SMT solvers. It is based on a non-determ...
Microprocessor pipelining is a well-established technique that improves performance and reduces powe...
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5970511&tag=1Microarchitectural refinements are...
AbstractWe apply algebraic tools for modelling microprocessors to the specification, implementation,...
technical reportWe present a systematic approach to decompose and incrementally build the proof of c...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2]...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2...
In microprocessors, achieving an efficient utilization of the execution units is a key factor in imp...
Subject of this thesis is the formal verification of pipelined microprocessors. This includes proces...
We present a systematic approach to decompose and incrementally build the proof of correctness of pi...
technical reportWe offer a solution to the problem of verifying formal memory models of processors b...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
The transition from single-core to multi-core processors has made multi-threaded software an importa...
Our reliance on the correct functioning of embedded systems is growing rapidly. Such systems are use...
The design of concurrent algorithms tends to be a long and difficult process. Increasing the number ...