This paper describes a novel low-power coding methodology for buses. Ultra deep submicron technology and system-on-chip have resulted in a considerable portion of power consumption on buses, in which the major sources of the power consumption are the transition activities on the signal lines and the coupling capacitances of the lines. In addition, we enter an era of considering variation of the effective coupling capacitances. We address power reduction including these phenomena by using variable length coding. Experimental results show the effectiveness of our methodology
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
Copyright © 2017 American Scientific Publishers. All rights reserved. Energy, delay and noise immuni...
In this paper we present a simplified model for deep submicron, on-chip, parallel data buses. Using ...
Abstruct- Technology trends and especially portable applications drive the quest for low-power VLSI ...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
A data-distribution and bus-structure aware methodology for the design of coding schemes for low-pow...
Now a day’s VLSI has become the backbone of all types of designs. Interconnect plays an increasing r...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and sy...
University of Minnesota Ph.D. dissertation. November 2008. Major: Electrical Engineering. Advisor: G...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and sy...
Abstract The energy dissipation associated with driving long wires accounts for a significant fracti...
[[abstract]]In this paper, we propose a bus encoding scheme to minimize coupling effects which cause...
We present a partial bus-invert coding scheme for power optimization of system level bus. In the pro...
The coupling capacitances between on-chip bus lines become dominant in deep-submicron technologies. ...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
Copyright © 2017 American Scientific Publishers. All rights reserved. Energy, delay and noise immuni...
In this paper we present a simplified model for deep submicron, on-chip, parallel data buses. Using ...
Abstruct- Technology trends and especially portable applications drive the quest for low-power VLSI ...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
A data-distribution and bus-structure aware methodology for the design of coding schemes for low-pow...
Now a day’s VLSI has become the backbone of all types of designs. Interconnect plays an increasing r...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and sy...
University of Minnesota Ph.D. dissertation. November 2008. Major: Electrical Engineering. Advisor: G...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and sy...
Abstract The energy dissipation associated with driving long wires accounts for a significant fracti...
[[abstract]]In this paper, we propose a bus encoding scheme to minimize coupling effects which cause...
We present a partial bus-invert coding scheme for power optimization of system level bus. In the pro...
The coupling capacitances between on-chip bus lines become dominant in deep-submicron technologies. ...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
Copyright © 2017 American Scientific Publishers. All rights reserved. Energy, delay and noise immuni...
In this paper we present a simplified model for deep submicron, on-chip, parallel data buses. Using ...