A data-distribution and bus-structure aware methodology for the design of coding schemes for low-power on-chip and interchip communication is presented. A general class of coding schemes for low power, termed transition pattern coding schemes, is introduced. The energy behavior of the schemes is mathematically analyzed in detail. Two algorithms are proposed for deriving such efficient coding schemes, which are optimized for desired bus structures and data distributions. Bus partitioning is proposed and mathematically analyzed as a way to reduce the complexity of the encoder/decoder
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
System on–chip design in deep submicron technology interconnects plays an important role in overall ...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and sy...
Abstract The energy dissipation associated with driving long wires accounts for a significant fracti...
In this paper we present a simplified model for deep submicron, on-chip, parallel data buses. Using ...
This paper describes a novel low-power coding methodology for buses. Ultra deep submicron technology...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
University of Minnesota Ph.D. dissertation. November 2008. Major: Electrical Engineering. Advisor: G...
Interconnects on deep submicron (DSM) buses incur significantly larger power dissipation, delay perf...
Now a day’s VLSI has become the backbone of all types of designs. Interconnect plays an increasing r...
With technology scaling, size of both transistor and interconnects are reduced. Power dissipation du...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
[[abstract]]In this paper, we propose a bus encoding scheme to minimize coupling effects which cause...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
System on–chip design in deep submicron technology interconnects plays an important role in overall ...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and sy...
Abstract The energy dissipation associated with driving long wires accounts for a significant fracti...
In this paper we present a simplified model for deep submicron, on-chip, parallel data buses. Using ...
This paper describes a novel low-power coding methodology for buses. Ultra deep submicron technology...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
University of Minnesota Ph.D. dissertation. November 2008. Major: Electrical Engineering. Advisor: G...
Interconnects on deep submicron (DSM) buses incur significantly larger power dissipation, delay perf...
Now a day’s VLSI has become the backbone of all types of designs. Interconnect plays an increasing r...
With technology scaling, size of both transistor and interconnects are reduced. Power dissipation du...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
[[abstract]]In this paper, we propose a bus encoding scheme to minimize coupling effects which cause...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
System on–chip design in deep submicron technology interconnects plays an important role in overall ...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and sy...