Analysis of process errors and production yield for surface mounted printed circuit assembly

Concurrent engineering in electronic manufacturing industries assures product quality through the integration of product and process design. To maximize the concurrent engineering effort, the fundamental understanding of the relationship between product and process quality, especially the process capabilities and propagation of in-process errors, must be better developed. This paper presents a process error model which is intended for production yield evaluation during the printed circuit design stage by considering the process errors in the device packaging, printed circuit board manufacturing, and assembly equipment process capability. An analysis of the effects of in-process errors in the pick-and-place process is described. The application of Monte Carlo simulation in estimating the surface mounted technology printed circuit assembly yield is also demonstrated