Process design for yield in deep submicron devices

Interaction between the manufacturing process and the circuit has become a major source of the yield loss in nanometer nodes of the current day semiconductor manufacturing. In this thesis author attempts to formalize a framework for both designers and process engineers to solve process and design interaction related yield problems. The process design for yield framework offers a systematic methodology for understanding these interactions and provides solutions while considering the implementation cost and manufacturability. The framework discussed in this thesis consists of three major stages. The first step is identifying the nature of the fails. In the second step, a relationship between chip parameters to the building block of the circuit—transistors, resistors, capacitors etc is established. The third step involves relating the devices to individual process modules and process steps. The novelty of current proposal is an increase in yield without either radically changing the process or re-doing the design, both of which are expensive. The experimental evidence towards applicability of the framework is provided through case study approach. The three case studies presented in here were taken from a high volume deep submicron semiconductor manufacturing environment. In the case study 1 and case study 2, yield loss mechanisms due to chip level parameters were studied. Through systematic analysis of the fail signature, a relationship between device parameters and the chip parameters was established. The device parameters were then related to process parameters. Solutions to yield problems were obtained by performing the cost vs. benefit analysis. In case study 3, functional fail mechanism was addressed. Using root mean square (RMS) methodology, a relationship between the process module and the functional fails was established. Individual process controls were evaluated and optimized by balancing cost of implementation with yield gain. The applicability of proposed framework is successfully proven in silicon. Author expects that process design for yield framework would bridge the knowledge gap that exists between the FAB-less design community and the integrated (semiconductor) device manufacturers (IDM)