Engineering design automation tool for yield learning model for IC packaging

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.Includes bibliographical references: p. 53-54.Issued also on microfiche from Lange Micrographics.The leading edge of semiconductor manufacturing is the high yield production of semiconductor devices of which integrated circuit packaging has a continuous increasing demand along with integrated circiut functionality. IC packaging manufacturing is subject to a yield learning cycle similar to that of IC manufacturing. The time-to-market period should therefore be optimally small. This necessitates the development of a yield prediction tool for package yield learning and thus optimizing the cycle time. In this research a methodology to predict the yield for package assemblies and a design automation tool has been developed and implemented. This yield learning model along with the automation tool has been used as a management tool for making yield predictions, resource allocations, understanding operating practices and providing what-if analysis. We developed a nonlinear spreadsheet-based model and tuned to each manufacturing line. We demonstrated the use of these models in industry to accurately predict the yield as a function of factor values, using a very small amount of data. We have experimentally validated our approach using the actual yield values obtained in the assembly line. Also, this research focuses on the cycle time issues for the yield model that we have developed for the packaging line. The number of lots processed in the line experience a time for which they are processed before they go on to the final stage This includes the processing time and the defect diagnosis time, which we have termed in as the defect diagnosis cycle time. We have suggested an algorithm for the determination of this defect diagnosis cycle time in the assembly line taking into consideration the waiting time issues in the line and its relation to the yield learning curve. We are interested here in this time because it in effect increases the rate of learning. The delay caused due to a defect, is cased by the variability in the operating environment. To significantly reduce the assembly cycle times, one must reduce that variability[1]