Cache Design for a Hardware Accelerated Sparse Texture Storage System

Hardware texture mapping is essential for real-time rendering. Unfortunately the memory bandwidth and latency often bounds performance in current graphics architectures. Bandwidth consumption can be reduced by compressing the texture map or by using a cache. However, the way a texture map occupies memory and how it is accessed a#ects the pattern of memory accesses, which in turn a#ects cache performance. Thus texture compression schemes and cache architectures must be designed in conjunction with each other