Run-Time Compaction of FPGA Designs

Controllers for partially reconfigurable FPGAs that are capable of supporting multiple independent tasks simultaneously need to be able to place designs at run--time when the sequence of tasks is not known in advance, or the designs are not fixed. As tasks arrive and depart the cells available for placement become fragmented, thereby affecting the controller's ability to place new tasks. The response times of tasks and the utilization of FPGA cells consequently suffers. In this paper, we describe and assess a task migration heuristic to alleviate the problems of external fragmentation. Our task compaction strategy moves the designs placed in a given region of the chip closer together by suspending the tasks and reloading their configuration bit--streams with new offsets. We show by simulation that significant performance improvements are possible, and that for reasonable assumptions about the relative lengths of the configuration delay and the service period of tasks, the penalty for r..