The development of FPGAs that can be programmed to implement custom circuits by modifying memory has inspired researchers to investigate how FPGAs can be used as a computational resource in systems designed for high performance applications. When such FPGA--based systems are composed of arrays of chips or chips that can be partially reconfigured, the programmable array space can be partitioned among several concurrently executing tasks. If partition sizes are adapted to the needs of tasks, then array resources become fragmented as tasks with varying requirements are processed. Tasks may end up waiting despite their being sufficient, albeit fragmented resources available. We examine the problem of repartitioning the system (rearranging a sub...
ARM-FPGA coupled platforms allow accelerating the computation of specific algorithms by executing th...
Abstract. Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the func...
The main goal of this project is to develop a framework of techniques to allow efficient hardware mu...
Field-programmable gate arrays (FPGAs) which allow partial reconfiguration at run time can be shared...
Partial rearrangement of executing tasks has been proposed as a means of alleviating the fragmentati...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
Aim of this paper is to define a scheduling of the task graph of an application that minimizes its t...
In this paper we present a novel scheduling technique for partially-reconfigurable FPGA-based system...
This paper proposes a new model for the partitioning and scheduling of a specification on partially ...
Controllers for partially reconfigurable FPGAs that are capable of supporting multiple independent t...
High-performance reconfigurable computing involves acceleration of significant portions of an ap-pli...
This paper proposes a new model for the partitioning and scheduling of a specification on partially ...
This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To faci...
International audienceField-programmable gate array (FPGAs) are classified as high efficient computa...
ARM-FPGA coupled platforms allow accelerating the computation of specific algorithms by executing th...
Abstract. Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the func...
The main goal of this project is to develop a framework of techniques to allow efficient hardware mu...
Field-programmable gate arrays (FPGAs) which allow partial reconfiguration at run time can be shared...
Partial rearrangement of executing tasks has been proposed as a means of alleviating the fragmentati...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
Aim of this paper is to define a scheduling of the task graph of an application that minimizes its t...
In this paper we present a novel scheduling technique for partially-reconfigurable FPGA-based system...
This paper proposes a new model for the partitioning and scheduling of a specification on partially ...
Controllers for partially reconfigurable FPGAs that are capable of supporting multiple independent t...
High-performance reconfigurable computing involves acceleration of significant portions of an ap-pli...
This paper proposes a new model for the partitioning and scheduling of a specification on partially ...
This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To faci...
International audienceField-programmable gate array (FPGAs) are classified as high efficient computa...
ARM-FPGA coupled platforms allow accelerating the computation of specific algorithms by executing th...
Abstract. Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the func...
The main goal of this project is to develop a framework of techniques to allow efficient hardware mu...