Strategies (TIN2006-03274)

The main goal of this project is to develop a framework of techniques to allow efficient hardware multitasking on dynamically reconfigurable FPGAs. The target architecture models range from commercial architectures such as Virtex, 1D reconfigurable, to academic architectures with very promising features, such as 3-dimensional ones. It also includes 2D architectures that nowadays focus the interest of many researchers. The set of techniques we want to develop will include enhanced versions of the basic set of scheduling strategies of a previous project, but now taking into account task data dependencies and task pre-emption. We will also study the allocation of space for task configuration and data on the different architecture models. Moreover, we will tackle the free space fragmentation problem and we will propose solutions involving local and global defragmentation processes. Finally, we will develop techniques to reduce the penalty due to the reconfiguration latency, such as a memory hierarchy and task prefetch and preload