Field-programmable gate arrays (FPGAs) which allow partial reconfiguration at run time can be shared among multiple independent tasks. When the sequence of tasks to be performed is unpredictable, the FPGA controller needs to make allocation decisions online. Since online allocation suffers from fragmentation, tasks can end up waiting despite there being sufficient, albeit noncontiguous, resources available to service them. The time to complete tasks is consequently longer and the utilisation of the FPGA is lower than it could be. It is proposed that a subset of the tasks executing on the FPGA be rearranged when to do so allows the next pending task to be processed sooner. Methods are described and evaluated for overcoming the NP-hard proble...
ARM-FPGA coupled platforms allow accelerating the computation of specific algorithms by executing th...
International audienceField-programmable gate array (FPGAs) are classified as high efficient computa...
Designing systems mapped onto FPGAs that foresee a dynamic reconfiguration of the application is a d...
The development of FPGAs that can be programmed to implement custom circuits by modifying memory has...
Partial rearrangement of executing tasks has been proposed as a means of alleviating the fragmentati...
In this paper we present a novel scheduling technique for partially-reconfigurable FPGA-based system...
Reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) are very popular in today's em...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
Aim of this paper is to define a scheduling of the task graph of an application that minimizes its t...
This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To faci...
In this dissertation, we focus our research on the problems related to efficient configurable resour...
This paper proposes a new model for the partitioning and scheduling of a specification on partially ...
Considering nowadays FPGAs, the reconfiguration time is a non-negligible element of reconfigurable c...
This paper proposes a new model for the partitioning and scheduling of a specification on partially ...
High-performance reconfigurable computing involves acceleration of significant portions of an ap-pli...
ARM-FPGA coupled platforms allow accelerating the computation of specific algorithms by executing th...
International audienceField-programmable gate array (FPGAs) are classified as high efficient computa...
Designing systems mapped onto FPGAs that foresee a dynamic reconfiguration of the application is a d...
The development of FPGAs that can be programmed to implement custom circuits by modifying memory has...
Partial rearrangement of executing tasks has been proposed as a means of alleviating the fragmentati...
In this paper we present a novel scheduling technique for partially-reconfigurable FPGA-based system...
Reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) are very popular in today's em...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
Aim of this paper is to define a scheduling of the task graph of an application that minimizes its t...
This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To faci...
In this dissertation, we focus our research on the problems related to efficient configurable resour...
This paper proposes a new model for the partitioning and scheduling of a specification on partially ...
Considering nowadays FPGAs, the reconfiguration time is a non-negligible element of reconfigurable c...
This paper proposes a new model for the partitioning and scheduling of a specification on partially ...
High-performance reconfigurable computing involves acceleration of significant portions of an ap-pli...
ARM-FPGA coupled platforms allow accelerating the computation of specific algorithms by executing th...
International audienceField-programmable gate array (FPGAs) are classified as high efficient computa...
Designing systems mapped onto FPGAs that foresee a dynamic reconfiguration of the application is a d...