Scheduling of Tasks with Precedence Delays and Relative Deadlines- Framework for Time-optimal Dynamic Reconfiguration of FPGAs

This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To facili-tate the design process we present an optimal schedul-ing algorithm using a very universal framework, where tasks are constrained by precedence delays and relative deadlines. The precedence relations are given by an oriented graph, where tasks are represented by nodes. Edges in the graph are related either to the minimum time or to the maximum time elapsed between the start times of the tasks. This framework is used to model the runtime dynamic reconfiguration, synchronization with an on-chip processor and simultaneous availabil-ity of arithmetic units and SRAM memory. The NP-hard problem of finding an optimal schedule satisfying the timing and resource constraints while minimizing the makespan Cmax, is solved using two approaches. The first one is based on Integer Linear Programming and the second one is implemented as a Branch and Bound algorithm. Experimental results show the effi-ciency comparison of the ILP and Branch and Bound solutions. Index Terms – Off-line scheduling, high–level syn-thesis, branch and bound, ILP, FPGA