Operation Scheduling in a Reconfigurable Computing Environment

We consider the problem of scheduling the operations of a data flow graph in a reconfigurable computing environment. In the recent years, FPGAs have become highly popular as a medium to rapidly prototype complex systems. As the FPGA technology improves in terms of speeds and the number of gates/chip, FPGAs are being used in system construction and not just for prototyping. Some innovations such as dynamic and partial reconfiguration of FPGAs has opened new doors to high-performance computing using limited amount of hardware. For example, the Dynamic Instruction Set Computer (DISC) allows a CPU to reconfigure its hardware dynamically depending on the set of instructions it is currently executing. Similarly, one can design an application-specific computer using dynamically reconfigurable FPGAs which use a limited number of FPGA chips to run a large computation within a time limit. In this paper, our intention is to describe the problem of operator scheduling in such a dynamically reconfi..