Gather-Scatter DRAM: In-DRAM Address Translation to Improve the Spatial Locality of Non-unit Strided Accesses

Many data structures (e.g., matrices) are typically ac-cessed with multiple access patterns. Depending on the layout of the data structure in physical address space, some access patterns result in non-unit strides. In ex-isting systems, which are optimized to store and access cache lines, non-unit strided accesses exhibit low spatial locality. Therefore, they incur high latency, and waste memory bandwidth and cache space. We propose the Gather-Scatter DRAM (GS-DRAM) to address this problem. We observe that a commodity DRAM module contains many chips. Each chip stores a part of every cache line mapped to the module. Our idea is to enable the memory controller to access multiple val-ues that belong to a strided pattern from different chip