A mostly-clean DRAM cache for effective hit speculation and self-balancing dispatch

Die-stacking technology allows conventional DRAM to be integrated with processors. While numerous opportunities to make use of such stacked DRAM exist, one promising way is to use it as a large cache. Although previous studies show that DRAM caches can deliver per-formance benefits, there remain inefficiencies as well as significant hardware costs for auxiliary structures. This paper presents two innovations that exploit the bursty nature of memory requests to streamline the DRAM cache. The first is a low-cost Hit-Miss Pre-dictor (HMP) that virtually eliminates the hardware overhead of the previously proposed multi-megabyte MissMap structure. The second is a Self-Balancing Dispatch (SBD) mechanism that dynam-ically sends some requests to the off-chip memory even though the request may have hit in the die-stacked DRAM cache. This makes effective use of otherwise idle off-chip bandwidth when the DRA