This paper presents an operating system managed die-stacked DRAM called i-MIRROR that mirrors high locality pages from the off-chip DRAM. Optimizing the problems of reducing cache tag area, reducing transfer bandwidth and improving hit latency altogether while using the die-stacked DRAM as hardware cache is extremely challenging. In this paper, we show that performance and energy efficiency can be obtained by software management of the die-stacked DRAM, which eliminates the need for tags, the source of aforemen-tioned problems. In the proposed scheme, the operating system loads pages from disks to the die-stacked DRAM on a page fault at the same time as they are loaded to the off-chip DRAM. Our scheme maintains the pages in the off-chip and...
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-h...
This article describes and evaluates a new approach to optimizing DRAM performance and energy consum...
In this paper, we present Bi-Modal Cache - a flexible stacked DRAM cache organization which simultan...
the tight integration of significant quantities of DRAM with high-performance computation logic. How...
Die-stacking is a new technology that allows multiple integrated circuits to be stacked on top of ea...
Abstract—Recent research advocates large die-stacked DRAM caches in manycore servers to break the me...
textContemporary DRAM systems have maintained impressive scaling by managing a careful balance betwe...
Abstract—This paper analyzes the trade-offs in architecting stacked DRAM either as part of main memo...
Abstract—Recent technology advancements allow for the integration of large memory structures on-die ...
As device technologies scale in the nanometer era, the current off-chip DRAM technologies are very c...
Die-stacking technology allows conventional DRAM to be integrated with processors. While numerous op...
DRAM memory systems require periodic recharging to avoid loss of data from leaky capacitors. These r...
<p>Over the past two decades, the storage capacity and access bandwidth of main memory have improved...
DRAM caches have shown excellent potential in capturing the spatial and temporal data locality of ap...
PosterDRAM vendors have traditionally optimized for low cost and high performance, often making desi...
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-h...
This article describes and evaluates a new approach to optimizing DRAM performance and energy consum...
In this paper, we present Bi-Modal Cache - a flexible stacked DRAM cache organization which simultan...
the tight integration of significant quantities of DRAM with high-performance computation logic. How...
Die-stacking is a new technology that allows multiple integrated circuits to be stacked on top of ea...
Abstract—Recent research advocates large die-stacked DRAM caches in manycore servers to break the me...
textContemporary DRAM systems have maintained impressive scaling by managing a careful balance betwe...
Abstract—This paper analyzes the trade-offs in architecting stacked DRAM either as part of main memo...
Abstract—Recent technology advancements allow for the integration of large memory structures on-die ...
As device technologies scale in the nanometer era, the current off-chip DRAM technologies are very c...
Die-stacking technology allows conventional DRAM to be integrated with processors. While numerous op...
DRAM memory systems require periodic recharging to avoid loss of data from leaky capacitors. These r...
<p>Over the past two decades, the storage capacity and access bandwidth of main memory have improved...
DRAM caches have shown excellent potential in capturing the spatial and temporal data locality of ap...
PosterDRAM vendors have traditionally optimized for low cost and high performance, often making desi...
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-h...
This article describes and evaluates a new approach to optimizing DRAM performance and energy consum...
In this paper, we present Bi-Modal Cache - a flexible stacked DRAM cache organization which simultan...