VL-CDRAM: variable line sized cached DRAMs

Many of the current memory architectures embed a SRAM cache within the DRAM memory. These architectures ex-ploit a wide internal data bus to transfer an entire DRAM row to the on-memory cache. However, applications exhibit a varying spatial locality across the different DRAM rows that are accessed and buffering the entire row may be waste-ful. In order to adapt to the changing spatial locality, we propose a Variable Line size Cached DRAM (VL-CDRAM) that can buffer portions of an accessed DRAM row. Our evaluation shows that the proposed approach is effective in not only reducing the energy consumption but also in im-proving the performance across various memory configura-tions