We propose to overcome the memory capacity limitation of GPUs with a Heterogeneous Memory Stack (HMS) that integrates Storage Class Memory (SCM) and DRAM in a 3D memory stack. By effectively utilizing the DRAM as a cache, the HMS addresses the latency, bandwidth, and energy challenges of the SCM. For workloads that mandate memory oversubscription, the HMS can capture a larger fraction of the memory footprint compared to an HBM, providing a significant performance uplift. To enable a performant DRAM cache architecture, we propose a DRAM cache bypass mechanism that avoids DRAM cache thrashing by 100,000 s of GPU threads. Furthermore, we propose a Tag Cache which uses part of L2 cache to hold tags of DRAM cachelines and reduce DRAM cache probe...
Graphics Processing Units (GPUs) and other throughput processing architectures have scaled performan...
General-purpose Graphics Processing Units (GPGPUs) have shown enormous promise in enabling high thro...
Part 2: Parallel and Multi-Core TechnologiesInternational audienceMemory access efficiency is a key ...
Current GPU computing models support a mixture of coherent and incoherent classes of memory operatio...
Advancements in packaging technology enable high-bandwidth 3D-DRAM that mitigates the memory bandwid...
Integrated Heterogeneous System (IHS) processors pack throughput-oriented General-Purpose Graphics P...
Pervasive use of GPUs across multiple disciplines is a result of continuous adaptation of the GPU a...
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-h...
Abstract—This paper presents an innovative memory management approach to utilize both 3D-DRAM and ex...
As device technologies scale in the nanometer era, the current off-chip DRAM technologies are very c...
Conventional compute and memory systems scaling to achieve higher performance and lower cost and pow...
GPU heavily relies on massive multi-threading to achieve high throughput. The massive multi-threadin...
Abstract. The memory wall (the gap between processing and storage speeds) remains a concern to compu...
Hybrid main memories composed of DRAM as a cache to scalable non-volatile memories such as phase-cha...
Abstract—With the SIMT execution model, GPUs can hide memory latency through massive multithreading ...
Graphics Processing Units (GPUs) and other throughput processing architectures have scaled performan...
General-purpose Graphics Processing Units (GPGPUs) have shown enormous promise in enabling high thro...
Part 2: Parallel and Multi-Core TechnologiesInternational audienceMemory access efficiency is a key ...
Current GPU computing models support a mixture of coherent and incoherent classes of memory operatio...
Advancements in packaging technology enable high-bandwidth 3D-DRAM that mitigates the memory bandwid...
Integrated Heterogeneous System (IHS) processors pack throughput-oriented General-Purpose Graphics P...
Pervasive use of GPUs across multiple disciplines is a result of continuous adaptation of the GPU a...
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-h...
Abstract—This paper presents an innovative memory management approach to utilize both 3D-DRAM and ex...
As device technologies scale in the nanometer era, the current off-chip DRAM technologies are very c...
Conventional compute and memory systems scaling to achieve higher performance and lower cost and pow...
GPU heavily relies on massive multi-threading to achieve high throughput. The massive multi-threadin...
Abstract. The memory wall (the gap between processing and storage speeds) remains a concern to compu...
Hybrid main memories composed of DRAM as a cache to scalable non-volatile memories such as phase-cha...
Abstract—With the SIMT execution model, GPUs can hide memory latency through massive multithreading ...
Graphics Processing Units (GPUs) and other throughput processing architectures have scaled performan...
General-purpose Graphics Processing Units (GPGPUs) have shown enormous promise in enabling high thro...
Part 2: Parallel and Multi-Core TechnologiesInternational audienceMemory access efficiency is a key ...