Add to ORKGAbstract—We consider the extent to which the bit-level repre-sentation of variables can be used to optimize hardware gener-ated by high-level synthesis (HLS). Two approaches to bit-level optimization are considered (individually and together): 1) range analysis, and 2) bitmask analysis. Range analysis aims to prede-termine min/max ranges for variables to reduce the bitwidth re-quired to represent variables in hardware. Bitmask analysis char-acterizes individual bits within a word as either constants (1 or 0), sign bits, or unknowns, where constants/don’t-cares permit hard-ware to be eliminated under certain conditions. Static compiler-based analysis is contrasted with dynamic profiling-based analy-sis in terms of their potential to impact a...
Field Programmable Gate Arrays (FPGAs) are now considered as a real alternative for Digital Signal P...
We propose a classification of high and low-level compiler optimizations to reduce the clock period,...
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area ...
High-level synthesis provides an easy-to-use abstraction for designing hardware circuits. However, s...
— In this paper we propose a methodology that takes into account bit-width to optimize area and powe...
High-level synthesis is a novel method to generate a RT-level hardware description automatically fro...
As the complexity of integrated circuit systems increases, automated hardware design from higher-lev...
In this paper we propose a methodology that takes into account bit-width to optimize area and power ...
Automated hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acce...
MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static ...
This paper addresses the problem of choosing different word-lengths for each functional unit in fixe...
Abstract—We consider the impact of compiler optimizations on the quality of high-level synthesis (HL...
International audienceField programmable gate arrays (FPGAs) are now considered as a real alternativ...
Using a high level language (HLL) to specify a computation for synthesis in ASIC or FPGA hardware re...
Automated hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acce...
Field Programmable Gate Arrays (FPGAs) are now considered as a real alternative for Digital Signal P...
We propose a classification of high and low-level compiler optimizations to reduce the clock period,...
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area ...
High-level synthesis provides an easy-to-use abstraction for designing hardware circuits. However, s...
— In this paper we propose a methodology that takes into account bit-width to optimize area and powe...
High-level synthesis is a novel method to generate a RT-level hardware description automatically fro...
As the complexity of integrated circuit systems increases, automated hardware design from higher-lev...
In this paper we propose a methodology that takes into account bit-width to optimize area and power ...
Automated hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acce...
MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static ...
This paper addresses the problem of choosing different word-lengths for each functional unit in fixe...
Abstract—We consider the impact of compiler optimizations on the quality of high-level synthesis (HL...
International audienceField programmable gate arrays (FPGAs) are now considered as a real alternativ...
Using a high level language (HLL) to specify a computation for synthesis in ASIC or FPGA hardware re...
Automated hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acce...
Field Programmable Gate Arrays (FPGAs) are now considered as a real alternative for Digital Signal P...
We propose a classification of high and low-level compiler optimizations to reduce the clock period,...
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area ...