Bit-Level Transformation and Optimization for Hardware Synthesis of Algorithmic Descriptions

As the complexity of integrated circuit systems increases, automated hardware design from higher-level abstraction is becoming more and more important. However, for many high-level programming languages, such as C/C++, the description of bitwise access and computation is not as direct as hardware description languages, and hardware synthesis of algorithmic descriptions may generate sub-optimal implement-tations for bitwise computation-intensive applications. In this paper we introduce a bit-level transformation and optimization approach to assisting hardware synthesis of algorithmic descriptions. We introduce a bit-flow graph to capture bit-value information. Analysis and optimizing transformations can be performed on this representation, and the optimized results are transformed back to the standard data-flow graphs extended with a few instructions representing bitwise access. This allows high-level synthesis tools to automatically generate circuits with higher quality. Experiments show that our algorithm can reduce slice usage by 29.8 % on average for a set of real-life benchmarks on Xilinx FPGAs. In the meantime, the clock period is reduced by 13.6 % on average, with an 11.4 % latency reduction. 1