Making HLS a Bit Wiser: From Standard High-Level Datatypes to Arbitrary Low-Level Bitwidths

High-level synthesis provides an easy-to-use abstraction for designing hardware circuits. However, standard datatypes available in high-level languages are over provisioned for typical applications, incurring unnecessary area overhead since the underlying FPGA hardware can support arbitrary bitwidths. We provide a bitwidth minimization (BWM) framework that analyzes and eliminates unused bits in the circuit's datapath and allows for the use of arbitrary width datatypes in the high-level source code. We then propose Sensei, an advisor that predicts the post-synthesis area savings brought about by reducing bitwidth and presents users with a ranking of program variables based on area impact. Together, these two contributions aim to bridge the gap between the over-provisioned datapaths of high-level languages and the arbitrary-width datapaths of low-level circuits.M.A.S