Feasibility of Using High-Level Synthesis in FPGA Design : Evaluating the Capabilities of Intel High-Level Synthesis Compiler

Field Programmable Gate Arrays (FPGA) have become vital in high-performance Digital Signal Processing (DSP) applications in embedded systems, but the development process of application-specific hardware is long and requires expertise on FPGA design and Hardware Description Languages (HDL). In recent years, High-Level Synthesis (HLS) has risen in popularity. It shortens the development time and simplifies the design work significantly by increasing the amount of abstraction between written code and the resulting hardware. The aim of this thesis was to evaluate the feasibility of using HLS as an alternative to traditional, Register Transfer Level (RTL) FPGA design. Since Intel is one of the world’s largest FPGA manufacturers along with Xilinx, studying the capabilities of the Intel HLS Compiler was chosen as the primary subject of the study. To perform an accurate comparison between RTL and high-level FPGA design, two nearly identical components for performing a matrix-matrix multiplication were developed. The other component was developed using the Verilog hardware description language and Intel Quartus FPGA design tools, while the other component was developed using C++ and Intel HLS Compiler. Then, the resource consumption and performance of the two different component implementations were compared. To provide more versatile results, comparison data was collected with different input data bit widths and different number of parallel multiply-accumulate (MAC) operations. It was discovered that in most cases, the HLS implementation used a lot more resources than the RTL implementation. With parameter values that the RTL implementation was optimised for, the results of the HLS implementation were significantly worse. On the other hand, the HLS implementation provided more consistent performance results with different parameters and even came ahead of the RTL implementation in some cases. It was concluded that while traditional FPGA design can achieve superior results in terms of both performance and resource consumption, the implementations might only be optimised for a narrow use case. Optimising an RTL design written with an HDL for different applications can take a significant amount of time and effort. Therefore, the Intel HLS Compiler may be an appropriate choice for projects that require a quick development of a medium-performance DSP component. The Intel HLS Compiler was deemed not suitable for implementing control logic or for very high-performance applications, such as high-throughput physical layer components