Using HLS for Acceleration of FPGA Development: A 3780-Point FFT Case Study

Manually designing hardware for fpga implementations is time consuming. Onepossible way to accelerate the development of hardware is to use high level syn-thesis (hls) tools. Such tools synthesizes a high level model written in a languagesuch as c++ into hardware. This thesis investigates hls and the efficacy of using hls in the hardware design flow. A 3780-point fast Fourier transform optimized for area is used to compare Vitis hls with a manual hardware implementation. Different ways of writing the highlevel model used in hls and their impacts in the synthesized hardware together with other optimizations is investigated. This thesis concludes that the results from the hls implementation are not comparable with the manual implementation, they are significantly worse. Further, high level code written from a non-hardware point of view needs to be rewritten from a hardware point of view to provide good results. The use of high level synthesis is not best used by designers from an algorithm or software background, but rather another tool for hardware designers. High level synthesis can be used as an initial design tool, allowing for quick exploration of different designs andarchitectures