Low vs High Level Programming for FPGA

From their introduction in the eighties, Field-Programmable Gate Arrays (FPGAs) have grown in size and performance for several orders of magnitude. As the FPGA capabilities have grown, so have the designs. It seems that current tools and languages (VHDL and (System)Verilog) do not match the complexity required for advanced digital signal processing (DSP) systems usually found in experimental physics applications. In the last couple of years several commercial High-Level Synthesis (HLS) tools have emerged, providing a new method to implement FPGA designs, or at least some parts of it. By providing a higher level of abstraction, new tools offer a possibility to express algorithms in a way which is closer to the mathematical description. Such implementation is understood by a broader range of people, and thus minimizes the documentation and communication issues. Several examples of DSP algorithms relevant for beam instrumentation will be presented. Implementations of these algorithms with different HLS tools and traditional implementation in VHDL will be compared