A testable design of programmable logic arrays with universal control and minimal overhead

AbstractIn this paper we propose a new technique for designing easily testable PLAs. Our design is a hybrid of the many existing testable designs of PLAs and therefore has almost all features of existing designs. These are (1) simple design, (2) high fault coverage, (3) easiliy implemented on existing design automation systems, (4) little or no degradation of PLA performance in normal operations, and (5) elimination of need for test pattern generation and fault simulation. In addition to these, we define the silicon area overhead, g, associated with a PLA as an objective function. We then find a solution such that g is minimized in our design. Thus the additional feature our PLA possesses is (6) “minimal” overhead. The technique consists of addition of some bit lines as well as a shift register for control of product-lines during test mode. The extra logic is added in such a manner that all easily testable features are maintained whereas the overall area of the extra logic is minimized. Using this design all multiple stuck-at faults, as well as all multiple extra and missing cross-point faults are detected