Design Automation and the Programmable Logic Array Macro

The Programmable Logic Array (PLA) macro is a physical structure which simpl8es LSZ chip design while yielding high density and good performance. Zn addition, the inherent order and regularity of this structure provide opportunities to speed design through automated logic documentation, design vergcution by computer simulation, and computer-automated physical design. In this paper a chip design methodology is described which is based on the use of PLA structures (or macros) within a chip. Logic functions in array form are speciJed in a compact notation that is automatically converted either to army personulization patterns or to conventional logic blocks for input to existing checking and testing softwure. Simulation of any logic urray is performed by a single program subroutine operating on these patterns. In addition, the simple, regular nature of the logic array lends itself to automutic generation of the layout geometries necessary to actually build the array on a silicon chip. Progrums developedfor these purposes and the PLA mucro design procedures are described in the context of an engineering design system