A method of test pattern generation for programmable logic arrays /

A method for PLA test pattern generation based on a branch and bound algorithm that exploits function monotonicity is presented. The algorithm makes irrevocable input assignments first, resulting in the efficient generation of compact test sets. In most cases there is no backtracking. An intelligent branching heuristic is presented. The algorithm handles extended fault models including crosspoint and delay faults. Heuristics which speed up test set generation and improve test set compaction are discussed.Results of tests on a wide range of benchmark PLAs are included