Digital Intensive Circuit Design Techniques for Enhancing Performance of Clock Generators and Data Converters

University of Minnesota Ph.D. dissertation. December 2014. Major: Electrical/Computer Engineering. Advisor: Chris Kim. 1 computer file (PDF); xi, 197 pages.Over the last few decades, the semiconductor industry have been developed along with the scaling of CMOS transistors. The reduced feature size makes it easy to integrate as many as digital logic and memory circuits within a limited die area. However, analog and mixed-signal circuit systems including clock generators (i.e. PLL, DLL and etc.) and data converters (i.e. ADC, TDC and etc.) have not fully utilized the beneficial transistor scaling since they have been mainly designed with critical analog circuit blocks such as amplifiers which require the use of large transistors to meet their analog performance criteria (i.e. gain, bandwidth and etc.). This thesis makes several contributions to the mixed-signal clock generators and data converters by proposing digital-intensive or all-digital circuit design techniques which facilitate the utilization of highly-digital mixed-signal circuit systems in a variety of applications ranging from high-performance microprocessors to compact and low-power biomedical and healthcare systems. Firstly, we present an adaptive PLL which can optimize microprocessor power and performance by automatically tracking supply noise sensitivity with the proposed closed-loop circuit including a digital bit-error monitor in Chapter 2. In Chapter 3 and 4, we propose novel quantization schemes of analog-to-digital conversion for the direct acquisition of extremely small physiological signals with sub-mV input range. By measuring the beat frequency (i.e. frequency difference) between the two VCO output clock frequencies driven by an input signal and a reference, we can detect sub-mV input signals with the ADC resolution of 6-to-7ENOB. Novel time amplifier concepts for digital PLL based clock generator circuits are presented in Chapter 5 and 6. In Chapter 5, a switched ring-oscillator based time amplifier with precise gain control and wide input range is presented. The proposed time amplifier has been implemented in a time amplifier based three-step TDC and used for achieving high time resolution and wide input range along with a fine Vernier delay line based TDC. In Chapter 6, a noise-shaping TDC has been implemented with an adaptive pulse train time amplifier. The high TDC resolution has been achieved by combining a noise-shaping gated-ring oscillator based TDC techniques and a pulse-train based time amplifier. The adaptive time amplifier has been used for achieving wide input range by adaptively controlling the time amplifier gain (i.e. high time amplifier gain with narrow input range and low gain with wide input range). Another type of digital PLL (i.e. bang-bang digital PLL) with a proposed noise-shaping fractional sub-sampler is described in Chapter 7. Digital PLL in-band noise is reduced with the sub-sampling operation and the spurs due to limit cycle of digital PLL are suppressed from the noise-shaping behavior of the proposed sub-sampler circuit. In the last topic of this thesis (Chapter 8), we propose an aging-tolerant digital PLL based on a dynamic element matched ring-oscillator DCO circuit. In-situ DCO aging monitor has been also included in the test-chip for the first time to evaluate the impact of different stress mechanisms on the digital PLL operation