Clock synthesizer design with analog and digital phase locked loop

As process technology has aggressively scaled, the demand for fast, robust computing has grown tremendously. With the rise of large scale data centers to handhold mobile devices, the desire for faster, low-power integrated inter-IC communication protocols is at an all-time high. This trend, together with the widespread presence of broadband Internet, multi-core CPU and system-on-chip designs have pushed the demand for data rate in wireless and wireline links into multi-Gbps ranges. In order to fulfill the increasing demand for high data rate links, the performance of the I/O channel needs to scale proportionally. But, due to the lag in interconnect scaling and PCB material improvements, the channel bandwidth has not scaled with data rates. The channel is therefore the biggest bottleneck in high-speed I/O communication links. In order to fulfill the demand of high-speed multi-Gigabit data transmission capacity, the system needs to incorporate robust, low-power fast-locking on-chip clocking circuits. The fundamental building block of every clocking circuit used in high-speed links is the Phase-Locked Loop (PLL). This thesis provides an in-depth analysis of basic analog PLL theory, architecture and transistor level design. The all-digital counterpart of the analog PLL will also be presented for its ultra low power and small footprint. The design and complete simulation result of a basic clock synthesizer circuit will be used as a design example for both the analog and digital PLL circuit design so that the readers will have in-depth understanding of the details of designing an on-chip PLL circuit. An overview of the high-speed communication scheme of the serial link will also be discussed to illustrate the importance of the PLL. It concludes by laying the motivation for future applications of PLLs and the need for further research in the area of low-power, high-fidelity fast-locking PLLs