A Study on Fully-Synthesizable All-Digit PLLs

The purpose of this research is to study fully-synthesizable clock generation circuits, which are widely used in most System on Chips (SoC) or modern digital systems. These clock generation circuits should generate a low-noise clock with low power consumption, and this makes the oscillator output noise reduction very important. Since phase-locked-loops (PLLs) are mostly used for the clock generation purpose, we first investigate all-digital PLLs (ADPLLs) to address design issues in conventional analog PLLs. However, current ADPLLs require custom circuit design and cannot fully take advantage of automated digital design flows. So the design considerations that should be made to leverage automated design flows and how to reduce the noise from the oscillator in fully-synthesizable ADPLLs are studied. I present a solution to this problem by implementing a simple digital phase detector, loop filter, and gated digitally controlled oscillator (DCO). This can greatly reduce not only the design complexity but the output noise of the ADPLL, which is verified with various simulations using SystemVerilog.U of I OnlyUndergraduate senior thesis not recommended for open access