Low-area and power-efficient on-chip clock reference generation

The advancement of modern one-chip applications, including system-on-chips (SoCs) and ultra-low-power systems such as wearables and internet-of-things (IoTs), has been the major driving force for the development of the integrated circuit industry over the past decade. One-chip reference generators are required by one-chip applications such as biomedical sensors, micro-controller units (MCUs), as well as high-speed input/output interfaces in SoCs. In addition to the power and volume constraints to ensure low-cost realization, one-chip applications typically operate across a wide range of frequencies, imposing challenging design requirements on the on-chip clock generators which are critical in timing coordination of the system. With aggressive scaling of the silicon technology improving transistor density of synthesized digital processors, clock generations with intensive analog/mixed-signal implementations have imposed obstacles to the overall scaling of power supply level, negating the overall benefits brought by the process scaling. This dissertation explores design techniques at both architecture and circuit level to achieve power- and volume-efficient designs without compromising the performance. In the first project, we propose an alternative integral path control using time-based techniques in type-II PLL. Leveraging the inherent integration from frequency to phase via a ring oscillator, the time-based integral loop eliminates the passive capacitor of the loop filter in conventional architecture, achieving a highly digital implementation that scales favorably with more advanced process. A prototype time-based PLL is implemented using a ring oscillator-based integrator (ROI). Fabricated in 65 nm CMOS LP process, the prototype PLL occupies an active area of only 0.0021 mm2 and operates across a supply voltage range of 0.6 V to 1.2 V, providing output frequencies ranging from 0.4 to 2.6 GHz. At 2.2 GHz output frequency, the PLL consumes 1.82 mW at 1 V supply voltage, and achieves 3.73 psrms integrated jitter. This translates to an FoMJ of -226.0 dB, which compares favorably with state-of-the-art designs while occupying the smallest reported active area. Next, we investigate the clock generators for ultra-low-power (ULP) systems for internet-of-thing (IoT) applications. RC relaxation oscillators (RCOs) are shown to achieve excellent frequency stability when generating clocks in kHz-MHz range, but are not very power efficient (5 μW/MHz). Their power efficiency further degrades at higher frequency due to additional complexity to maintain temperature stability, limiting the applications for MCUs operating at hundreds of MHz. Hence, we propose to use a ring oscillator (RO) based digital PLL to multiply the RCO frequency to the desired operating frequencies. Inherently, RO shows superior phase noise performance and power efficiency over RCO, and the PLL loop bandwidth needs to be lowered in order to mitigate the noise contribution from the RCO. Consequently, the output RO dominates the output clock phase noise beyond the bandwidth. To achieve a power efficient design, hybrid PLL architecture is employed with varactor-based analog proportional control and digital integral control using delta-sigma modulator (DSM) DAC. Switched resistor technique is employed to implement post-loop filter for DSM DAC in an area-efficient manner. Fabricated in 65 nm CMOS technology, the prototype HPLL achieves 2.3 psrms period jitter at 70 MHz and consumes 406 _W. The output oscillator evaluates to an excellent FoM of >162 dB across wide range of frequency from 45 to 75 MHz. Finally, we address the area consumption for low-bandwidth PLL applications. In conventional type-II PLL architecture, reducing the bandwidth is achievable through drastic scaling of proportional path gain, which degrades the tracking capability of the PLL. On the other hand, the loop filter capacitor inevitably increases in order to maintain loop stability, consequently increasing the overall chip area consumption in low-bandwidth setting. To address the challenges observed in conventional PLL, we propose an alternative DPLL architecture using delay modulating clock buffer, which reduces the closed-loop bandwidth with the same hardware complexity of a conventional DPLL counterpart. Such architecture is particularly suitable in applications with RCO as the reference clock, as the DPLL is capable of operating directly with the internal capacitor charging node of RCO. Fabricated in 65 nm CMOS process, the prototype DPLL generates 48-330 MHz output frequencies from a reference clock in the range of 0.5-5 MHz. The DPLL occupies an active area of 125 μm by 125 μm, and achieves ±0.33% period jitter while consuming 63.5 μW at an output frequency of 240 MHz. This translates to an excellent power efficiency of 0.26 μW/MHz at 0.8 V supply voltage, which compares favorably with the state-of-the-art.U of I OnlyAuthor requested U of Illinois access only (OA after 2yrs) in Vireo ETD syste