Design, Implementation, and Testing of a 25 Gb/s Pipelined Memory Switch Buffer in Full-custom CMOS

Among the switch buffer architectures, shared buffering achieves the best memory utilization and optimum link throughput, but requires the use of high-throughput memories. Pipelined memory is a novel organization for building such high-throughput memories, featuring simplified control and very efficient VLSI implementation. In this work we designed a pipelined memory with a throughput of 25 Gbits/s (16 Gbits/s in the worst case), enough for 8 incoming and 8 outgoing links at gigabit per second rates. Full-custom design techniques were employed to achieve small area and high speed. The full-custom implementation of the pipelined memory pays off the long development time, as our implementation is 4 times smaller and 3 times faster than the pipelined memory of a semicustom switch chip that was recently designed by our research group. Besides the pipelined memory that was implemented, three other floorplan organizations were investigated which can be used for pipelined memories of different specifications. A test chip containing the pipelined memory and semi-custom control and interface circuits was fabricated. This chip, although it revealed some minor design errors, operates correctly for clock frequencies of up to 80MHz, consuming 2.75 Watts