A novel FPGA architecture supporting wide, shallow memories

The FPGAs of today are being used to implement large, system-sized circuits. Systems often require significant memory resources, and vendors have responded to these needs by embedding block memories onto their FPGAs. A proportion of these user circuits are communications-based, which have slightly different requirements from standard systems. Most notably, these circuits often contain wide data signals that must be buffered and processed efficiently and quickly. Wide signals also often originate from recently developed high-speed I/O that allow FPGAs to communicate with higher frequency circuits. This thesis investigates an architecture designed to implement wide, shallow memories on an FPGA. Under the proposed architecture, existing configuration memory normally used to control the connectivity pattern of the FPGA is made user accessible. Typically, not all the switch blocks in an FPGA are. used to transport signals. By adding only a modest amount of circuitry, the configuration memory in these unused switch blocks can be used to implement wide, shallow buffers and other similar memory structures. The size of FPGA required to implement a benchmark circuit that makes use of the wide, shallow memories, is 20 percent smaller than a standard memory architecture. In addition, the benchmark circuit is on average 40 percent faster in the proposed architecture. To get access to this memory additional circuitry must first be added. The extra transistors required will result in an area and speed overhead, even for circuits that do not make use of the new wide, shallow memories. The overhead of this circuitry was measured to be a 36 percent increase in overall FPGA area, and a 5 percent increase in critical path delay.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat