Add to ORKGThis paper describes the design of the Packet Buffer Chip. Packet Buffers are FIFO queues used for buffering packets and synchronizing a Switch Fabric (SF) and its associated Fiber Optic Links (FOLS) in the Broadcast Packet Switching Network. This chip will be fabricated in 2.0 UM CMOS technology
In a wide area network that uses store-and-forward technology, a packet switch buffers incoming data...
This paper describes an innovative packet-switched network architecture hardware prototype, designed...
This paper describes a high performance packet switching network that can be used to provide voice, ...
This paper describes the design of the Packet Switch Element Chip, one of the components of a high s...
This paper describes the design of the Packet Switch Element Chip, one of the components of a high s...
This paper describes the design of the PP3 packet processor chip. PP3 is one of the four component c...
ABSTRACT: Switch chips are building blocks for computer and communication systems. Switches need int...
A key technique for reducing packet blocking in optical switches is by temporarily buffering packets...
This paper describes the design of a Broadcast Translation Circuit chip. The Broadcast Translation C...
In this paper, we comparatively evaluate two photonic packet switch architectures with WDM-FDL buffe...
This thesis presents a number of new approaches for designing fast, scalable queuing structures in ...
This thesis describes a family of VLSI chips designed to link a number of processors on a one-to-one...
Summary This paper proposes a dynamic packet buffer management algorithm for a protocol processor in...
The broadcast packet network is a form of communications network based on high speed packet switches...
With the rapid development of optical communications, transport of data over fiber channel can now r...
In a wide area network that uses store-and-forward technology, a packet switch buffers incoming data...
This paper describes an innovative packet-switched network architecture hardware prototype, designed...
This paper describes a high performance packet switching network that can be used to provide voice, ...
This paper describes the design of the Packet Switch Element Chip, one of the components of a high s...
This paper describes the design of the Packet Switch Element Chip, one of the components of a high s...
This paper describes the design of the PP3 packet processor chip. PP3 is one of the four component c...
ABSTRACT: Switch chips are building blocks for computer and communication systems. Switches need int...
A key technique for reducing packet blocking in optical switches is by temporarily buffering packets...
This paper describes the design of a Broadcast Translation Circuit chip. The Broadcast Translation C...
In this paper, we comparatively evaluate two photonic packet switch architectures with WDM-FDL buffe...
This thesis presents a number of new approaches for designing fast, scalable queuing structures in ...
This thesis describes a family of VLSI chips designed to link a number of processors on a one-to-one...
Summary This paper proposes a dynamic packet buffer management algorithm for a protocol processor in...
The broadcast packet network is a form of communications network based on high speed packet switches...
With the rapid development of optical communications, transport of data over fiber channel can now r...
In a wide area network that uses store-and-forward technology, a packet switch buffers incoming data...
This paper describes an innovative packet-switched network architecture hardware prototype, designed...
This paper describes a high performance packet switching network that can be used to provide voice, ...