Chapter 5 Concurrent VLSI Architecture Group

The Concurrent VLSI architecture group is developing technology to enable the construction of large, scalable parallel computer systems. For the past year, this work has focused on three areas: high-speed signaling, router architecture, and construction of a prototype M-Machine parallel computer. 5.1 High-Speed Signaling We are developing technology that increases the bandwidth per pin of CMOS chips by two orders of magnitude. We have developed several prototype signaling systems. The latest system demonstrates 4Gb/s signaling over a pair of I/O pads in a standard 0.25um CMOS technology. Equalization enables these signaling rates to be used over cables up to 10m in length. Our current design is power efficient, requiring only 90mW per link, and requires only 0.01mm 2 of chip area. This low-power and area make it possible to put hundreds of these high-speed pads on a conventional CMOS chip enabling single-chip multicomputer routers with bandwidth approachin