Maintaining Scalability of Test Generation using Multi-core Shared Memory Systems

Taking advantage of multi-core architectures can provide significant improvement for many design automation problems. However, the parallelization procedure introduces challenges such as workload duplication, limited search space exploration and race contention among different threads. In this work we propose a parallel framework for ATPG using shared memory multi-core systems that supports test generation for both single-detect and multiple-detect fault models. The framework follows a two-epoch approach, each focusing on a different category of faults, during which a test seed generation is followed by compatibility merging. Various optimization techniques are incorporated in each epoch, designed to achieve higher speed-up for the overall test generation procedure without impacting much the test set size. A cluster-based approach is also presented extending the proposed framework to consider multiple-detect fault models without affecting its efficiency. The obtained experimental results demonstrate increased speed-up rates compared to the state-of-the-art multi-core based tools while, at the same time, the test inflation problem is restrained. For the multiple-detect extension, these properties are maintained despite the increased workload and the additional constraint of retaining the number of detections for each fault while merging.© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. S. Hadjitheophanous, S. N. Neophytou and M. K. Michael, "Maintaining Scalability of Test Generation using Multi-core Shared Memory Systems," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, doi: 10.1109/TVLSI.2019.294718