Exploiting Shared-Memory to Steer Scalability of Fault Simulation using Multicore Systems

Current and future multicore architectures can significantly accelerate the performance of test automation procedures depending on the underlying architecture and the scalability of their algorithms. This work proposes a new parallel methodology targeting the fault simulation problem, for shared memory multi-core systems, that maintains scalability with the increase of the number of cores. The method is based on a simple single thread process that allows focusing on the optimization of the parallelization process in different dimensions. Additionally, a number of optimizations are incorporated in the approach to control fault dropping and to avoid necessary work. The reported experimental results, for both random and deterministic test sets, demonstrate the scalability of the method. As the number of cores increases, the reported speed-up increases proportionally, where comparable recent methods report saturation or even reduction of the obtained speed-up© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. S. Hadjitheophanous, S. N. Neophytou and M. K. Michael, "Exploiting Shared-Memory to Steer Scalability of Fault Simulation using Multicore Systems," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. doi: 10.1109/TCAD.2018.2855131 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8410458&isnumber=691705