Power efficient SOC design techniques for advanced Finfet process technology

The Semiconductor industry has excelled the electronics market in providing high speed, power efficient, smart and reliable electronic devices. Transistors are made more and more powerful, with the advent of various process technology nodes and methods, which has led to the invention of high speed, single/multi-core microprocessors, Application Specific Integrated Circuits, Field Programmable Gate Array and Memory chips. One such powerful and efficient process technology is the Fin Field Effect Transistor (FinFET) technology. This technology features with high performance, low leakage, less area and minimum supply voltage and it helps to integrate more and more functionality on a single IC (Integrated Circuit) chip. The properties of FinFETs will be presented in this dissertation; a comparison is made between the planar MOSFETs and FinFET devices. FinFET device sizing methodology is explained with experimental results. Stacked designs were not considered among the planar MOSFETs due to the ill effects of stack or body effect. However stacked designs are advantageous among the FinFET devices due to its unique geometrical structure and it is proven by experiments in this research study. The proposed stacked design style is simulated and compared with a conventional non-stacked design, and obtained an average power reduction of 57% and area reduction by 37%, using an industrial 7nm FinFET technology library. Nevertheless, this design style incurs a delay trade-off of 42%. These research findings were submitted to “International Symposium on Integrated Circuits IEEEISIC 2016 Conference”, Singapore. The research paper was accepted and presented in the Conference, and is included in the Conference Proceedings and IEEE Xplore. This research paper is also included in this dissertation.Master of Science (Integrated Circuit Design