Comparative study of nano-scale standard CMOS versus finfet

Planar Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have been leading the semiconductor industry for many decades. To continue Moore’s law, new structures and devices have been developed. One such innovation is Fin Field Effect Transistors (FinFET), which has gained significant interest in the silicon process, which can replace the traditional planar devices. FinFETs, in particular, aim at regaining considerable control of the gate over the channel of the transistor. There are many tradeoffs between these two technologies in terms of power consumption, cost of fabrication, speed, and performance. Complementary Metal-Oxide Semiconductor (CMOS) uses additional and symmetrical pairs of p and n-type MOSFETs for logic functions. Two notable characteristics of CMOS devices are high noise immunity and low static power consumption. After the introduction of a 3-dimensional transistor, most of the errors which were holding back the CMOS technology have been the answer while scaling the sizes from micro to nano. The nanoscale transistor uses a vertical gate that looks like a fin and thus named as FINFET. To change the parameters of parasitic elements, an additional layer was incorporated between 1st metal and the structure of the transistor. FinFET devices have been proposed as promising alternatives to conventional bulk CMOS devices at the nanoscale because of their unique properties, such as improved channel controllability, a high ON, and OFF current proportion decreased short-channel impacts, and relative resistance to gate line-edge unpleasantness. In this thesis, the comparative study of CMOS and FinFET is investigated considering ring oscillator as a benchmark, which is implemented using both FinFET and CMOS technologies while comparing average power consumption and propagation delay of the models. Here, the ring oscillator is implemented in spice using the simulator as HSPICE. The corresponding is done between the ring oscillator designed in a 16nm process of CMOS and FinFET. The results are compared based on the average power, fall time, rise time, and the frequency of the oscillator, which illustrates the superiority of FinFETs over planar MOS devices. Many researchers have been investigating to develop novel structures to reduce the sizes into the sub-nanometer regime further while overcoming the drawbacks of conventional devices, and one such promising alternatives are Gate-All-Around (GAA) FET, which is still under developmental stages