Considerations for ultimate CMOS Scaling

Abstract—This review paper explores considerations for ul-timate CMOS transistor scaling. Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted. Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results. Index Terms—Complementary metal-oxide semiconductor (CMOS), FinFET, mobility, nanowire, silicon on insulator (SOI), strain. I