This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template architecture. Our framework permits to write a parallel application by using a shared memory model. It deals with the consistency of shared data, with no need of hardware coherence protocol, but uses a software model to properlyallsynchronize the local copies with the shared memory image. This idea can be applied both to a scratchpad-based architecture or a cache-based one. The architecture is synthesizable with standard IPs, such as the softcores and interconnect elements, which may be found in any commercial FPGA toolset
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) a...
Current chip multiprocessors (CMP) have mostly been designed by replicating sequential/single core p...
The single core processor stagnated due to four major factors. (1) The lack of instruction level par...
This paper presents a framework to design a shared memory multiprocessor on a programmable platform....
To build a shared-memory programming model for FPGAs, a fast and highly parallel method of accessing...
To build a shared-memory programming model for FPGAs, a fast and highly parallel method of accessing...
Cache coherence and memory consistency are of the most decisive and challenging issues in the design...
In this paper we discuss the development of two emulation platforms for transactional memory systems...
Recent technology advances in integrated electronics offer the ability to add more and more transist...
Field-Programmable Gate Arrays (FPGAs) systems now comprise many processing elements that are proce...
Abstract—The capacity of FPGA devices has reached the 1-million-LUT level, which provides space to a...
In this paper we present a rapid prototyping platform on a single Field Programmable Gate Array (FPG...
Porting software to different platforms can require modifications of the application. One of the iss...
In single processor architectures, computationally-intensive functions are typically accelerated usi...
FPGA densities have continued to follow Moore’s law and can now support a complete multiprocessor sy...
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) a...
Current chip multiprocessors (CMP) have mostly been designed by replicating sequential/single core p...
The single core processor stagnated due to four major factors. (1) The lack of instruction level par...
This paper presents a framework to design a shared memory multiprocessor on a programmable platform....
To build a shared-memory programming model for FPGAs, a fast and highly parallel method of accessing...
To build a shared-memory programming model for FPGAs, a fast and highly parallel method of accessing...
Cache coherence and memory consistency are of the most decisive and challenging issues in the design...
In this paper we discuss the development of two emulation platforms for transactional memory systems...
Recent technology advances in integrated electronics offer the ability to add more and more transist...
Field-Programmable Gate Arrays (FPGAs) systems now comprise many processing elements that are proce...
Abstract—The capacity of FPGA devices has reached the 1-million-LUT level, which provides space to a...
In this paper we present a rapid prototyping platform on a single Field Programmable Gate Array (FPG...
Porting software to different platforms can require modifications of the application. One of the iss...
In single processor architectures, computationally-intensive functions are typically accelerated usi...
FPGA densities have continued to follow Moore’s law and can now support a complete multiprocessor sy...
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) a...
Current chip multiprocessors (CMP) have mostly been designed by replicating sequential/single core p...
The single core processor stagnated due to four major factors. (1) The lack of instruction level par...