Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures

Many embedded architectures provide indirect addressing modes with autoincrement /decrement arithmetic. Since these architectures generally do not feature an indexed addressing mode, automatic variables must be accessed by allocating address registers and performing address arithmetic. Subsuming address arithmetic into auto-increment/decrement arithmetic improves both the performance and size of the generated code. Our objective in this paper is to provide a method for comprehensively analyzing the performance benefits and hardware cost resulting from an auto-increment/decrement feature that varies from \Gammal to +l, and a file of k address registers in an address generator. We provide this method via a parameterizable optimization algorithm that operates on a procedure-wise basis. We present two sets of experimental results based on selected benchmark programs: (1) the values of l and k beyond which there is little or no improvement in performance, and (2) the values of l and k whic..