Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture

Since most DSP applications access large amount of data stored in the memory, a DSP code generator must minimize the addressing overhead. In this paper, we propose a method for addressing optimization in loop execution targeted toward DSP processors with autoincrement /decrement feature in their address generation unit. Our optimization methods include a multi-phase data ordering and a graph-based address register allocation. The proposed approaches have been evaluated using a set of core algorithms targeted towards the TI TMS320C40 DSP processor. Experimental results show that our system is indeed more effective compared to a commercial optimizing DSP compiler. 1 Introduction Most DSP processors' address generation units (AGU) have more than one address registers with autoincrement /decrement capability. Addressing optimization can be achieved via data ordering and address register allocation. Data ordering determines the order of data stored in the memory. Address register allocat..