Unified instruction reordering and algebraic transformations for minimum cost offset

DSP processors have address generation units that can perform address computation in parallel with other operations. This feature reduces explicit address arithmetic instructions, often required to access locations in the stack frame, through auto-increment and decrement addressing modes, thereby decreasing the code size. Decreasing code size in embedded applications is extremely important as it directly impacts the size of on-chip program memory and hence the cost of the system. Effective utilization of auto-increment and decrement modes requires an intelligent placement of variables in the stack frame which is termed as "offset assignment". Although a number of algorithms for efficient offset assignment have been proposed in the literature, they do not consider possible instruction reordering to reduce the number of address arithmetic instructions. In this paper, we propose an integrated approach that combines instruction reordering and algebraic transformations to reduce the number of address arithmetic instructions. The proposed approach has been implemented in the SUIF compiler framework. We conducted our experiments on a set of real programs. and compared its performance with that of Liao's heuristic for Simple Offset Assignment (SOA), Tie-break SOA, Naive offset assignment, and Rao and Pande's algebraic transformation approach