Instructions executed by the processor are dynamically dead if the values they produce are not used by the program. Executing such useless instructions can potentially slow-down program execution and waste power. The goal of this work is to quantify and understand the occurrence of dynamically dead instructions (DDI) for programs compiled using modern compilers for the most relevant contemporary architectures. We expect our extensive study to highlight the issue of DDI and to play a critical role in the development of compiler and/or architectural techniques to avoid DDI execution at runtime. In this thesis, we introduce our novel GCC&ndashbased instrumentation and analysis framework to determine DDI during program execution. We present the...
The trend towards smaller transistor technologies and lower operating voltages stresses the hardwar...
The time-predictable design of computer architectures for the use in (hard) real-time systems is bec...
Pipelined microprocessors allow the simultaneous execution of several machine instructions at a time...
Instructions executed by the processor are dynamically dead if the values they produce are not used ...
We observe a non-negligible fraction---3 to 16% in our benchmarks ---of dynamically dead instruction...
At present there exist three main schools of thought for improving single-threaded program performan...
We describe Dead Value Information (DVI) and introduce three new optimizations which exploit it. DVI...
In their pursuit of faster code, compilers invoke increasingly more complex optimizations. Along wit...
In recent years, with only small fractions of modern processors now accessible in a single cycle, co...
A processor executes the full dynamic instruction stream in order to compute the final output of a p...
Current processors employ aggressive prediction mechanisms to improve performance and reduce power. ...
This paper explores the use of dynamic compilation for continuing execution even if one or more of t...
Program redundancy analysis and optimization have been an important component in optimizing compiler...
When a new computer architecture or a new method of code generation is proposed, the improvement in...
Many program verification, testing and performance prediction techniques rely on analysis of statica...
The trend towards smaller transistor technologies and lower operating voltages stresses the hardwar...
The time-predictable design of computer architectures for the use in (hard) real-time systems is bec...
Pipelined microprocessors allow the simultaneous execution of several machine instructions at a time...
Instructions executed by the processor are dynamically dead if the values they produce are not used ...
We observe a non-negligible fraction---3 to 16% in our benchmarks ---of dynamically dead instruction...
At present there exist three main schools of thought for improving single-threaded program performan...
We describe Dead Value Information (DVI) and introduce three new optimizations which exploit it. DVI...
In their pursuit of faster code, compilers invoke increasingly more complex optimizations. Along wit...
In recent years, with only small fractions of modern processors now accessible in a single cycle, co...
A processor executes the full dynamic instruction stream in order to compute the final output of a p...
Current processors employ aggressive prediction mechanisms to improve performance and reduce power. ...
This paper explores the use of dynamic compilation for continuing execution even if one or more of t...
Program redundancy analysis and optimization have been an important component in optimizing compiler...
When a new computer architecture or a new method of code generation is proposed, the improvement in...
Many program verification, testing and performance prediction techniques rely on analysis of statica...
The trend towards smaller transistor technologies and lower operating voltages stresses the hardwar...
The time-predictable design of computer architectures for the use in (hard) real-time systems is bec...
Pipelined microprocessors allow the simultaneous execution of several machine instructions at a time...