AbstractIn this paper we describe a network invariant for all configurations of the Futurebus+ Cache Coherence Protocol. The network invariant was computed with PAX and verified by a model checker. Using this invariant we are able to prove a specification of cache coherence correct for an arbitrary number of components on a single bus of the system. This specification includes a progress property not proven yet. We show how the result for the single bus system can be extended to tree-shaped systems. This is, as far as we know, the first uniform proof of the protocol with multiple data-buses
This paper presents a cache coherence solu-tion for multiprocessors organized around a single time-s...
In one embodiment, a cache comprises a cache memory and a cache control circuit coupled to the cache...
Computer architects are now studying a new generation of chip architectures that may integrate hundr...
AbstractIn this paper we describe a network invariant for all configurations of the Futurebus+ Cache...
This paper presents a case study for automatic verifi-cation using the Communicating Sequential Proc...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
Abstract—We propose an architectural design methodology for designing formally verifiable cache cohe...
In this paper we present a cache coherence protocol for multistage interconnection network (MIN)-bas...
this paper we present an analytical model of a ring-based shared-memory multiprocessor operating the...
Parallel applications exhibit a wide variety of memory reference patterns. Designing a memory archit...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
The use of private caches in a multiprocessor system causes inconsistency of the shared data among t...
This paper presents a cache coherence solu-tion for multiprocessors organized around a single time-s...
In one embodiment, a cache comprises a cache memory and a cache control circuit coupled to the cache...
Computer architects are now studying a new generation of chip architectures that may integrate hundr...
AbstractIn this paper we describe a network invariant for all configurations of the Futurebus+ Cache...
This paper presents a case study for automatic verifi-cation using the Communicating Sequential Proc...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
Abstract—We propose an architectural design methodology for designing formally verifiable cache cohe...
In this paper we present a cache coherence protocol for multistage interconnection network (MIN)-bas...
this paper we present an analytical model of a ring-based shared-memory multiprocessor operating the...
Parallel applications exhibit a wide variety of memory reference patterns. Designing a memory archit...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
The use of private caches in a multiprocessor system causes inconsistency of the shared data among t...
This paper presents a cache coherence solu-tion for multiprocessors organized around a single time-s...
In one embodiment, a cache comprises a cache memory and a cache control circuit coupled to the cache...
Computer architects are now studying a new generation of chip architectures that may integrate hundr...