A Fixed-Point Model of a Distributed Memory Consistency Protocol

this paper we present an analytical model of a ring-based shared-memory multiprocessor operating the IEEE P1596 Standard Coherent Interface (SCI) [3] and we assume an implementation of the protocol on the default unidirectional ring network. Full details of the protocol may be found in [2, 3], for example, but we note the key point which is that, in the absence of a shared bus for broadcasting coherency information, the sharers of a cache line are represented explicitly in the form of a sharing list. We demonstrate the use of this model by comparing the performance of two internal node architectures when the protocol is being used as an interconnect medium for multiple bus-based multiprocessors. To date, the only analytical model relevant to SCI that we are aware of is that of [5] which uses an M/G/1 model for analysing slotted ring networks, suitably adapted for a subset of the SCI traffic. The paper does not address SCI cache coherency, however, and so does not model the message traffic generated by each node to maintain a coherent global memory. Our approach is based on that of [4] for modelling bus-based coherency protocols; it differs in its characterisation of memory usage and in the way it models ring traffic and queueing for the cache and memory. 1.1 Workload Assumption