A New Cache Protocol Based On The Order Free Consistency Memory Model

Computer architects are now studying a new generation of chip architectures that may integrate hundreds of processing cores and memory banks on a single chip with novel in-terconnect technologies. A key challenge lies in the design and development of an efficient on-chip shared memory organization for these future many-core architectures. New ap-proaches need to be developed to address this challenge by overcoming the scalability and power limitations imposed by past work on cache coherence for symmetric multiprocessors. In addition, the theoretical foundation for these new coherence protocols need to be based on memory consistency models with a well-defined and programmer-friendly operational semantics. We believe that many-core processors represent a qualitative shift from past shared-memory architectures, thereby motivating a fresh look at coherence protocols in conjunction with memory models. In this paper, we revisit the notions of “uniprocessor dependences ” and “multiprocessor memory coherence”, both of which are fundamental assumptions in the Sequential Consis-tency (SC) model and other SC-derived memory consistency models 1. We propose a ne